Vertical mosfet transistor, in particular operating as a selector in nonvolatile memory devices

ABSTRACT

A vertical MOSFET transistor is formed in a body of semiconductor material having a surface. The transistor includes a buried conductive region of a first conductivity type; a channel region of a second conductivity type, arranged on top of the buried conductive region; a surface conductive region of the first conductivity type, arranged on top of the channel region and the buried conductive region; a gate insulation region, extending at the sides of and contiguous to the channel region; and a gate region extending at the sides of and contiguous to the gate insulation region.

RELATED APPLICATIONS

The present application is a continuation of co-pending U.S. patentapplication Ser. No. 11/411,982, filed on Apr. 26, 2006.

BACKGROUND OF INVENTION

1. Field of Invention

The subject of the present invention is a vertical MOSFET transistor, inparticular operating as a selector in nonvolatile memory devices.

The following description relates to a MOSFET transistor designed tooperate as selector for a phase-change memory, without, however, beinglimited to this type of application. In particular, the MOSFETtransistor according to the invention can be advantageously used alsofor other types of nonvolatile memories or other common-source-regionapplications.

2. Description of the Related Art

As is known, phase-change memories (PCMB) exploit the characteristics ofmaterials that have the property of switching between two phases thathave different electrical characteristics. For example, these materialscan switch between an amorphous, disorderly phase and a crystalline orpolycrystalline, orderly phase, and the two phases are associated toresistivities of markedly different values.

Currently, the alloys of group VI of the periodic table, such as Te orSe, referred to as calcogenides or calcogenic materials, mayadvantageously be used in phase-change memories. The currently mostpromising calcogenide is formed by a Ge, Sb, and Te alloy (Ge₂Sb₂Te₅),which is currently widely used for storing information in overwritabledisks.

In phase-change memories comprising calcogenic elements as storageelements, the memory cells are arranged in rows and columns, asillustrated in FIG. 1. The memory array 1 of FIG. 1 comprises aplurality of memory cells 2, arranged in the crossing points betweenrows 6 (also referred to as wordlines) and columns 5 (also referred toas bitlines) and each of which includes a memory element 3 of aphase-change type and a selection element 4.

In each memory cell 2, the memory element 3 has a first terminalconnected to an own wordline 6 and a second terminal connected to afirst conduction terminal of an own selection element 4. The selectionelement 4 has a second terminal connected to a bitline 5. In anothersolution, the memory element 3 and the selection element 4 of each cell2 can be exchanged.

Currently, as selection elements bipolar transistors, planar MOStransistors, or diodes have been proposed.

A method of manufacturing a phase-change memory device including a diodeas a selection element is described in US 200310219924. Another methodfor obtaining a memory comprising a bipolar transistor as a selectionelement is described in.

Phase-change memories using selectors made as bipolar components havethe problem that they dissipate even when they are in the non-selectedor off state thereby, as a whole, giving rise to a non-negligibleconsumption. Phase-change memories that use selectors made with planarMOS technology have the problem that they occupy a non-negligible area.

BRIEF SUMMARY OF THE INVENTION

One embodiment of the invention provides a MOSFET transistor that willsolve the problems of known devices, in particular as regardsdissipation and occupied area.

According to the present invention, a vertical MOSFET transistor, amemory array, and the corresponding methods of manufacturing areprovided as defined in claims 1, 10, 13 and 19, respectively.

One embodiment of the present invention provides a vertical MOSFETtransistor that includes a body of semiconductor material having asurface. Positioned in the body is a buried conductive region of a firstconductivity type; a channel region of a second conductivity type,arranged on top of the buried conductive region; and a surfaceconductive region of the first conductivity type, arranged on top of thechannel region and the buried conductive region. A gate insulationregion extends at sides of and contiguous to the channel region; and agate region extends at sides of and contiguous to the gate insulationregion.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

For an understanding of the present invention, preferred embodimentsthereof are now described, purely by way of non-limiting example, withreference to the attached drawings, wherein:

FIG. 1 is a circuit diagram of a known array of phase-change memorycells;

FIGS. 2-4 show cross-sections regarding an embodiment of the invention,in successive process steps;

FIG. 5 shows a top plan view of the structure of FIG. 4;

FIGS. 6-12 are cross-sections similar to FIG. 4, in successive processsteps;

FIG. 13 is a horizontal cross-section of a part of the structures ofFIGS. 14 and 15;

FIG. 14 is a cross-section similar to FIG. 12, in a subsequentmanufacturing step;

FIGS. 15-17 are cross-sections of another embodiment of the invention,in successive manufacturing steps;

FIG. 18 is a cross-section perpendicular to FIG. 17, taken along sectionline XVIII-XVIII of FIG. 17;

FIG. 19 is a top plan view of the structure of FIG. 18;

FIG. 20 is a cross-section of another embodiment of the invention;

FIG. 21 is a cross-section of a different embodiment of the invention;and

FIG. 22 represents a system according to an embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

The following figures show the cross section through a wafer 13 formedinitially by a substrate 15 of monocrystalline silicon, here of P type.In particular, the left-hand part of the wafer 13 (first area 10)regards the manufacture of a vertical MOSFET transistor, while theright-hand part (second area 11) regards the manufacturing of a standardMOSFET planar transistor.

With reference to FIG. 2, electrical-insulation regions are provided inthe second area II, within the substrate 15, here using an STI(Shallow-Trench Insulation) technique. To this end, in a per se knownmanner, a pad-oxide layer 16 is first grown or deposited, then a firstnitride layer 17 is deposited, the layers 16 and 17 are removedselectively, and a trench etch is performed. The trenches thus obtainedare filled with dielectric material so as to form insulation regions 18.

Next (FIG. 3), the first nitride layer 17 is removed and a maskedimplantation of dopant ions of an N type is performed only in the firstarea 10 so as to form a buried layer 19 of an N+ type.

Then (FIG. 4), a second nitride layer 20 is deposited. The secondnitride layer 20 and the pad-oxide layer 16 are shaped in the first area10 so as to form a mask (hard mask 24) having the shape desired for thechannel region (here square). Next, the substrate 15 is etched in thefirst area 10, where exposed, as far as the buried layer 19, therebyforming a pillar 21 (as highlighted in the top view of FIG. 5). The etchbrings about also a thinning of the hard mask 24, on account of thefinite selectivity of the etch.

Next (FIG. 6), without removing the mask 24, a thermal oxidation isperformed so as to grow a gate-insulation layer 22 on the walls of thepillar 21 and on the free surface of the buried layer 19.

Then (FIG. 7), a polysilicon layer, of N+ type, is deposited. Thepolysilicon layer can be doped directly in situ or subsequently and isthen removed for the excess portion, for example via a CMP(Chemical-Mechanical Polishing) step (which is interrupted on the secondnitride layer 20). Thus, it is aligned vertically to the hard mask 24and forms a lateral gate region 23 which surrounds the pillar 21.

Next, the second nitride layer 20 (FIG. 8) is selectively removed andthen the pad-oxide layer 16 is removed so eliminating the remainingportion of the hard mask 24.

Then, a surface oxidation is performed so forming a sacrificial-oxidelayer 25 both on the first area 10 and on the second area 11. Theremoval of the mask 24 leaves, on the surface of the first area 10, arecess 27 which is not filled by the sacrificial-oxide layer 25. Next,in the top portion of the pillar 21, a masked implantation of dopantions of N+ type is performed, thereby forming a vertical drain region 26underneath the sacrificial-oxide layer 25 and on top of a portion of thepillar 21 defining a channel region 29.

Next (FIG. 10) spacers 28 are provided on the edge of the recess 27. Tothis end, in a per se known manner, a silicon-oxide layer (or asilicon-nitride layer) is deposited, and is dry etched so as to removeit from the horizontal portions of the surface of the wafer 13. Thespacers 28 are useful for providing a slight margin in regard to thedrain/gate short-circuits, above all when titanium or cobalt silicidesare used.

Then (FIG. 11), standard steps for manufacturing MOSFET transistors areperformed. In particular, in the second area 11, the sacrificial-oxidelayer 25 is removed, a gate-oxide layer 30 is grown, and a polysiliconlayer is deposited and shaped to form a gate region 31. During removalof the sacrificial-oxide layer 25 and definition of the polysiliconlayer, the first area 10 is exposed to the treatments and its planaritypreserves the morphology thereof.

A gate-insulation layer 32 is then provided, which surrounds the gateregion 31, and spacers 33 are provided, for example of silicon nitride,at the sides of the gate region 31.

Next (FIG. 12), N+ implantations are performed in the second area 11 toform source and drain regions 34. Then, in both of the areas 10 and 11,the exposed portions of the oxide layers 25, 30 and 32 are removed; asilicidation is performed, with formation of regions of silicide (forexample, titanium silicide); in particular, silicide regions 35 a areformed on top of the source and drain regions 34, silicide regions 35 bare formed on top of the gate region 31, silicide regions 35 c areformed on top of the vertical drain region 26, and silicide regions 35 dare formed on top of the lateral gate region 23. In this way, in thefirst area 10 a vertical transistor 40 is present, which includes thevertical drain region 26, the channel region 29 with vertical currentflow, underneath the vertical drain region 26, the buried layer 19,defining a source region, and the lateral gate region 23, surroundingthe pillar 21 and extending on the top the buried layer 19. Thegate-insulation layer 22 insulates electrically the vertical drainregion 26, the channel region 29 and the buried layer 19 from thelateral gate region 23. In the second area 11 a planar MOS transistor 45is present, which includes the source/drain regions 34 and the gateregion 31.

The source region (buried layer 19) can be shared by other adjacentvertical transistors 40 or form part of a single vertical transistor 40(in this case, the masked implantation for forming the buried layer 19uses a suitable mask to obtain the formation of one or more buriedregions 19 having appropriate shape, size and position, and verticalinsulations must be provided between the various vertical transistors40). The width of the vertical transistor 40 is defined by the perimeterof the pillar 21 obtained by etch and can be thus controlled accurately.

Next, contacts are provided towards the various conductive regions.

FIG. 13 shows a top view on the first area 10, in the case of an arrayof vertical transistors 40, usable as selection elements in aphase-change memory array, as described hereinafter. As may be noted,the pillars 21 (the silicided regions 35 c whereof, associated to thevertical-drain regions 26, are visible in FIG. 13) are aligned alongrows. Source contact regions 41 are formed between each row of pillars21 by the surfacing portions of the substrate 15, which are not removedduring the etching for defining the pillars 21 (designated by 42 in FIG.14) and are doped with an N+ dopant (for example, while forming thesource and drain regions 34). The source contact regions 41 are moreovercoated on the top by silicide regions 35 e. The source contact regions41 are electrically insulated from the lateral gate regions 23 byportions of the gate insulation layers 22.

On top of the vertical transistors 40 of FIG. 13, the phase-changememory elements are then provided, which, in this application, comprisea heating element and a calcogenic element.

FIG. 14 shows a first embodiment wherein a heating element is formed ontop of a vertical transistor 40, in a second level. Here, a firstdielectric material layer 46 (for example, of silicon oxide) isdeposited on top of the wafer 13 and etched to form vias 47 for thecontacts. In particular, in the first area 10 a via 47 extends on top ofthe vertical drain region 26 as far as the silicide region 35 c and thevia is filled by a contact 48 (here formed by a double Ti/TiN layer andby tungsten); in the second area 11, vias 47 extend as far as thesilicide regions 35 a overlying the source/drain regions 34 and thesilicide regions 35 b overlying the gate region 31.

A second dielectric material layer 49 (for example, silicon nitride) anda third dielectric material layer 50 (for example, silicon oxide) aredeposited on top of the first dielectric layer 46. A glue layer 55 isdeposited on top of the layers 49, 50, and the layers 49, 50 and 55 areetched in the first area 10 on top of the vertical transistor 40 so asto form a via 51 extending as far as the contact 48. The walls of thevia 51 are coated with a spacing layer 52, for example of siliconnitride. Next, a resistive layer 53 (for example, of TiSiN, TiAlN orTiSiC) is sputtered, preferably by CVD (Chemical Vapor Deposition), andthe via 51 is closed by a filling material 54, for example siliconoxide, preferably by ALD (Atomic-Layer Deposition). The structure isthen planarized, for example via CMP, to remove the portions of thelayers 52, 53, 54 projecting from the via 51. In this way, the remainingportions of the resistive layer 53 form a ring-shaped heater.

FIG. 15 illustrates, instead, an embodiment wherein the heating element53 is formed directly on top of a vertical transistor 40. In thisembodiment, the first dielectric material layer 46, the via 47 and thecontact 48 are consequently absent; the contacts towards the transistorare formed subsequently.

With reference to the embodiment of FIG. 15, a memory layer 60, acalcogenic material layer (for example, Ge₂Sb₂Te₅), and a cap layer 61(for example, Ti_(x)Al_(y)N_(z), Ti_(x)Si_(y)N_(z) or Ti_(x)N_(y)) arethen deposited in succession (FIG. 16). The layers 61, 60 and 55 arethen defined, forming bitlines 59 that extend parallel to the plane ofthe drawing (as viewed in FIG. 19). While defining the bitline 59, theadhesive material 55 is completely removed from the second area 11.

Next, a sealing layer 62, for example, of silicon nitride, and a fourthdielectric material layer 63, for example of silicon oxide, aredeposited and planarized so as to coat completely the layers 60 and 61.Then, the fourth dielectric material layer 63 is planarized via CMP.

Next (FIG. 17), first and second openings 65 a and 65 b are made in thefirst area 10 and in the second area 11, respectively, via two separatedetches. Specifically, in the first area 10, the openings 65 a traversethe entire fourth dielectric material layer 63 and the sealing layer 62,reaching the cap layer 61. In the second area 11, the openings 65 btraverse the fourth dielectric material layer 63, the sealing layer 62,the third dielectric material layer 50 and the second dielectricmaterial layer 49 and reach the silicide regions 35 a, 35 b. Theopenings 65 a, 65 b are then coated by a barrier layer 66, for exampleof TaN/Ta, and filled by depositing a metal layer 67, here Cu. Afterplanarization of the wafer 13, the structure illustrated in FIG. 17 isthus obtained, which is then subjected to the typical final steps. As aresult, a plurality of memory elements 68 is obtained, each of which isarranged on top of a respective vertical transistor 40 that operates asselection element.

FIG. 18 shows a section perpendicular to that of FIG. 17, taken alongthe line XVIII-XVIII. In particular, in FIG. 18, the bitlines 59 formedby the layers 60, 61 and by the underlying portions of the glue layer 55may be noted.

FIG. 19 shows a top plan view of the structure of FIGS. 17 and 18, withsome layers removed for sake of clarity. In particular, FIG. 19 showsthe buried source resistance Rsl, i.e., the resistance existing alongthe buried layer 19 between the channel region 29 and each portion ofsubstrate 42 (see also FIG. 17).

In this case, the buried source resistance Rsl is equal to:R_(Sl)≈ρ*ln(1+2*h/d)/(2*t)≈0.25*ρ_(N+1) /twhere ρ is the resistivity of the buried layer 19, t its thickness (seeFIG. 17), h the length traversed by the current along the buried layer19, and d the minimum width of the current path (see FIG. 19).

The total resistance Rt encountered by the current coming from thechannel region 29 and directed towards the source contact region 41 ishence equal to Rsl+Rs2, where Rs2 is the source vertical resistance,i.e., the resistance encountered by the current along the substrateportions 42.

To reduce the total resistance Rt, it is possible to perform an N+source-line implantation, as illustrated in FIG. 20. This implantationcan be performed as dedicated implantation of an N+ type or exploitingthe N-well implant normally performed during the fabrication of planarMOSFETs. In either case, N+ regions 70 connect the source contact region41 to the buried layer or region 19.

According to another embodiment, it is possible to exploit an N+substrate underneath the substrate 15, when this is present. Thispossibility is illustrated in FIG. 21, which represents an area of thewafer 13 underlying the buried layer 19 where an N+ substrate 71 ispresent, having, for example, a doping level of approximately 10¹⁹at/cm². In this case, in an initial manufacturing step of the wafer 13,a sub-source implantation is performed so as to connect the N+ substrate71 to the buried layer 19. For example, phosphorus can be used at animplantation dose of 10¹⁴ at/cm² with an energy of between 300 and 1000keV to form a sub-source layer 72 of N+ type. Next, an annealing isperformed so as to reduce any possible damage of the silicon.

In this case, the resistance Rss between the buried layer 19 and the N+substrate 71 is equal to:R _(SS)=ρ_(N+) *t1/(d*(d+t1))≈ρ_(N+) /dwhere ρ_(N+) is the resistivity of the sub-source layer 72 and d is theminimum width of the current path (see FIG. 19). In this embodiment thecurrent path is indicated by dashed arrows in FIG. 21.

Yet a further possibility consists in maintaining the standard Psubstrate 15 (portion of substrate 42) and forming a vertical PMOS. Inthis case, however, the reduced mobility of the holes would require agreater overdrive (namely, the source-gate voltage necessary for turningon the device) to obtain the same currents and hence a higher gatevoltage or, alternatively, a larger perimeter (with a consequentincrease in the area occupied).

The advantages of the vertical transistor described are the following.First, the vertical transistor is practically as compact as knowntransistors (15F² as against 10F² of PNP bipolar junction transistors,where F is the minimum lithographic dimension that can be obtained forthe specific used technology), but uses just two dedicated masks anddoes not present any dissipation when it is not selected. As compared toFinFET transistors, the present vertical transistor has the samecompactness but uses fewer dedicated masks (two, instead of three orfour).

The described vertical transistor has a much greater driving capacity(three or four times) as compared to planar MOSFETs, for a same area.

The process steps necessary for manufacturing the vertical transistorcan be included conveniently in a CMOS process between the wellimplantations and the gate-oxide growth.

The described vertical transistor can be readily integrated in arraystructures and can hence advantageously be used in phase-change memoriesas a selection element.

With reference to FIG. 22, a description of a portion of a system 500according to an embodiment of the present invention now follows. Thesystem 500 can be used in wireless devices such as, for example, a PDA(personal digital assistant), a laptop or portable computer withwireless capacity, a web tablet, a wireless telephone, a pager, a devicefor sending messages instantaneously, a digital music player, a digitalcamcorder, or other devices that can be suited for transmitting and/orreceiving information in wireless mode. The system 500 can be used inany one of the following systems: a WLAN (wireless local-area network)system, a WPAN (wireless personal-area network) system, or a cell phonenetwork, even though the scope of the present invention is not limitedin this connection.

The system 500 can include a controller 510, an input/output device I/O520 (for example a keypad or a display), a memory 1, a wirelessinterface 540, and a SRAM (static random-access memory) 560, connectedtogether via a bus 550. A battery 580 can supply the system 500 in oneembodiment. It is emphasized that the scope of the present invention isnot limited to embodiments that have some or all of these components.

The controller 510 can comprise, for example, one or moremicroprocessors, digital-signal processors, microcontrollers, or thelike. The memory 1 can be used for storing messages transmitted by asystem 500 or received thereby. The memory 1 can optionally be used alsofor storing instructions that are executed by the controller 510 duringoperation of the system 500, and can be used for storing user data. Theinstructions can be stored as digital information, and the user data, asdescribed herein, can be stored in one section of the memory as digitaldata and, in another section, as analog data. In another example, agiven section at a time can be labeled and store digital information,and then can be re-labeled and reconfigured for storing analoginformation. The memory 1 can be provided with one or more types ofmemory. For example, the memory 1 can comprise a volatile memory (anytype of random-access memory) and a nonvolatile memory such as a flashmemory and/or a crosspoint memory.

The I/O device 520 can be used for generating a message. The system 500can use the wireless interface 540 for transmitting and receivingmessages to and from a wireless communication network with aradiofrequency (RF) signal. Examples of wireless interfaces 540 caninclude an antenna or a wireless transceiver, such as a dipole antenna,even though the scope of the present invention is not limited thereto.Furthermore, the I/O device 520 can supply a voltage correlated to whatis stored either as digital output (if digital information has beenstored) or as analog information (if analog information has beenstored).

Even though an example of a wireless application has been providedabove, embodiments of the present invention can also be used innon-wireless applications.

Finally, it is clear that numerous modifications and variations can bemade to the vertical transistor described and illustrated herein, allfalling within the scope of the invention, as defined in the attachedclaims. In particular, even though the foregoing description refers tothe manufacture of a vertical NMOS transistor, by appropriatelymodifying the dopants and starting materials, it is possible to providealso PMOS transistors, using the same process sequence.

Furthermore, even though the structure of the illustrated verticaltransistor has an approximately axial symmetry, with the gate insulationregion (gate-insulation layer 22) completely surrounding the channelregion 29 and with the lateral gate region 23 completely surrounding thegate insulation region, it is also possible to use a solution whereinboth the lateral gate region 23 and the gate-insulation layer 22 arearranged only on one side of the channel region 29 or on two oppositesides thereof (for example, with the channel region 29 formed by aregion elongated in the direction perpendicular to the plane of FIG.12), and other insulating regions are present for guaranteeing thenecessary electrical insulation between the various regions.

Even though the silicide regions 35 c-35 e are useful to reduce theresistance, in some applications, for example in the case of technologythat does not envisage silicided regions, they can be omitted.

As regards the fabrication of a phase-change memory, the structure ofthe heater 53 can also differ with respect to that illustrated, and theheater 53, instead of having the ring conformation illustrated(ring-shaped memory region formed by the intersection between theresistive layer 53 and the memory layer 60), can have an elongated(wall-like) shape or any other suitable shape. Likewise, the region ofmemory formed by the layer 60 can be configured differently; forexample, it can be made according to the minitrench technique (memorylayer 60 deposited in trenches formed in the fourth layer of dielectricmaterial 63 and shared by two adjacent memory cells) or according to thelance technique (memory layer 60 deposited in openings formed in thefourth layer of dielectric material 63 and provided with spacers forreducing the area of the openings to sublithographic dimensions).

It is moreover pointed out that the glue layer 55 is not essential andmay be absent.

Finally, the vertical transistors 40 can be used as selection elementsfor different types of memory, which use elements for storinginformation based upon physical mechanisms other than the phase changeof the PCMs.

All of the above U.S. patents, U.S. patent application publications,U.S. patent applications, foreign patents, foreign patent applicationsand non-patent publications referred to in this specification and/orlisted in the Application Data Sheet, are incorporated herein byreference, in their entirety.

From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

What is claimed is:
 1. A memory cell comprising: a vertical transistorcomprising a body of semiconductor material having a surface; a buriedconductive region of a first conductivity type positioned in the body; achannel region in the body, the channel region having a top and abottom, all of the bottom being in contact with the buried conductiveregion; a gate insulation region extending at sides of and contiguous tothe channel region; and a gate region extending at sides of andcontiguous to the gate insulation region wherein the buried conductiveregion further extends under the gate region, the buried conductiveregion and the gate region being insulated electrically from one anotherby a dielectric material layer; a phase change memory element coupled toa surface conductive region of the vertical transistor with aring-shaped heater; and a dielectric material within an interior of thering-shaped heater wherein the surface conductive region is of the firstconductivity type, and is in the body and arranged on top of the channelregion and the buried conductive region; wherein the ring-shaped heateris coupled to the surface conductive region through a multiple layercontact, the multiple layer contact comprising a via formed verticallyin a dielectric layer, the via filled by a plurality of materials toform the multiple layer contact.
 2. The memory cell of claim 1, whereinthe dielectric material fills the interior of the ring-shaped heater. 3.The memory cell of claim 1, wherein the buried conductive region is asource region, and the surface conductive region is a drain region. 4.The memory cell of claim 1, wherein the gate insulation regioncompletely laterally surrounds the channel region, and the gate regioncompletely laterally surrounds the gate insulation region.
 5. The memorycell of claim 1, wherein the gate insulation region and the gate regionextend on two sides of the channel region.
 6. The memory cell of claim1, wherein the buried conductive region, the channel region and at leastpart of the surface conductive region comprise monocrystalline material,and at least part of the gate region comprises polycrystalline material.7. The memory cell of claim 1, wherein the surface conductive regioncomprises a first semiconductor material region and a first metalsilicide region arranged on top of the first semiconductor materialregion.
 8. The memory cell of claim 1, wherein the gate region comprisesa second semiconductor material region and a second metal silicideregion, the second metal silicide region being arranged on top of thesecond semiconductor material region.
 9. The memory cell of claim 1,further comprising an electric contact region extending from the surfaceof the body as far as the buried conductive region, at sides of andseparated from the gate region.
 10. A memory cell comprising: a verticaltransistor including a body of semiconductor material having a surface;a buried conductive region of a first conductivity type positioned inthe body; a channel region in the body, the channel region having a topand a bottom, all of the bottom being in contact with the buriedconductive region; a surface conductive region of the first conductivitytype in the body and arranged on top of the channel region and theburied conductive region; a gate insulation region extending at sides ofand contiguous to the channel region; and a gate region extending atsides of and contiguous to the gate insulation region; and a phasechange memory element coupled to the surface conductive region of thevertical transistor with a ring-shaped heater; wherein the ring-shapedheater is coupled to the surface conductive region through a multiplelayer contact, the multiple layer contact comprising a via formedvertically in a dielectric layer, the via filled by a plurality ofmaterials to form the multiple layer contact.
 11. The memory cell ofclaim 10, further comprising a dielectric material within an interior ofthe ring-shaped heater.
 12. The memory cell of claim 10, wherein thegate insulation region completely laterally surrounds the channelregion, and the gate region completely laterally surrounds the gateinsulation region.
 13. The memory cell of claim 10, wherein the gateinsulation region and the gate region extend on two sides of the channelregion.
 14. The memory cell of claim 10, wherein the buried conductiveregion further extends under the gate region, the buried conductiveregion and the gate region being insulated electrically from one anotherby a dielectric material layer.
 15. The memory cell of claim 10, whereinthe surface conductive region comprises a first semiconductor materialregion and a first metal silicide region arranged on top of the firstsemiconductor material region.
 16. The memory cell of claim 10, whereinthe gate region comprises a second semiconductor material region and asecond metal silicide region, the second metal silicide region beingarranged on top of the second semiconductor material region.
 17. Amemory cell comprising: a vertical transistor including a body ofsemiconductor material having a surface; a buried conductive region of afirst conductivity type positioned in the body; a channel region in thebody, the channel region having a top and a bottom, all of the bottombeing in contact with the buried conductive region; a surface conductiveregion of the first conductivity type in the body and arranged on top ofthe channel region and the buried conductive region; a gate insulationregion extending at sides of and contiguous to the channel region; and agate region extending at sides of and contiguous to the gate insulationregion, the gate region comprising a first semiconductor material regionand a first metal silicide region, the first metal silicide region beingarranged on top of the first semiconductor material region; and a phasechange memory element coupled to the surface conductive region of thevertical transistor; wherein the phase change memory element is coupledto the surface conductive region at least through a multiple layercontact, the multiple layer contact comprising a via formed verticallyin a dielectric layer, the via filled by a plurality of materials toform the multiple layer contact.
 18. The memory cell of claim 17,wherein the surface conductive region comprises a second semiconductormaterial region and a second metal silicide region arranged on top ofthe second semiconductor material region.
 19. The memory cell of claim17, wherein the gate insulation region completely laterally surroundsthe channel region, and the gate region completely laterally surroundsthe gate insulation region.
 20. The memory cell of claim 17, wherein theburied conductive region further extends under the gate region, theburied conductive region and the gate region being insulatedelectrically from one another by a dielectric material layer.